Energy Efficient Transistors

author: Alan Seabaugh, University of Notre Dame

Description

Major technological shifts in solid-state device technology have typically been associated with improvements in device energy efficiency. This was true in the transition from vacuum tubes to bipolar transistors in the 1950s, and then again from bipolar transistors to MOSFETs in the 1970s. The next technological revolution will similarly stem from an improvement in energy efficiency at the device or at the circuit level. This lecture will explore ways in which new materials and transistors can extend the performance of electronic systems.

Categories

Top: Technology: Electronics

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*Slides*
0:00	- Announcement
2:01	Energy-Efficient Transistors
3:13	University of Notre Dame - 1
3:34	University of Notre Dame - 2
4:05	University of Notre Dame - 3
5:03	Notre Dame Nanofabrication Facility
6:20	Nanofabrication Facility - Opens 2010 - 1
6:31	Nanofabrication Facility - Opens 2010 - 2
6:47	Research team
7:09	Notre Dame Research 2007
8:04	Energy-Efficient Transistors
9:00	Natural selection for electron devices
11:54	Power Density Doubling Every Four Years
15:11	Natural selection for electron devices - survival of the most energy-efficient
16:02	Metal oxide semiconductor field-effect transistor (MOSFET) - 1
18:27	Metal oxide semiconductor field-effect transistor (MOSFET) - 2
19:55	Au-WS2 nanotube
21:00	WS2 tubes nanobuds, Remskar, Virsek, Jesih, Nanolett. submitted 2007
21:24	Size Comparison: Si MOSFET vs. MoS2 nanotube
22:08	65 nm Node 0.494 mm2 6-transistor-SRAM Cellsize comparison with WS2 fullerine
22:20	Die micrograph (5.7 x 6.6 mm2) Intel 44 Mbit ultra-low-power SRAM
23:05	Dynamic Power Dissipation
25:33	Complimentary MOS (CMOS) Power Dissipation
28:37	Subthreshold swing sets the minimum active power dissipation in MOSFETs
30:59	Energy-Efficient Transistors Outline
31:08	Interband Tunnel Junction
33:20	Field-effect Zener tunnel transistor
34:00	Low-Subthreshold-Swing Tunnel Transistor Technology Approach
35:39	Tunneling Current in Si p+n+ Junctions
36:55	Engineering Subthreshold Swing
38:33	Maximizing tunnel current
38:55	Tunnel Transistors vs. Scaled CMOS
39:56	Rapid Melt Growth of Ge Tunnel Junctions
41:09	Ramp up melt forms
41:17	Ge tunnel diode current-voltage characteristics vs. rapid-melt-growth anneal
41:59	Ge tunnel diode peak current densities vs. annealing temperatures with a 50 nm Si3N4 cap.
42:32	Optical micrographs showing the dependence of surface morphology on the presence or absence of a cap during rapid melt growth of p+Ge.
42:52	Diapozitiv37
43:48	Ge TD electron beam pattern 2007
44:23	First sub-60 mV/dec tunnel transistor
45:08	Energy-Efficient Transistors (summary)
46:21	Acknowledgements

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